1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to various methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming etching process.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In some applications, fins for FinFET devices are formed such that the fin is vertically spaced apart from and above the substrate with an isolation material positioned between the fin and the substrate. One prior art technique for forming a FinFET device having such an arrangement is generally referred to as a BOTS (Bottom Oxidation Through STI) and will generally be described with reference to FIGS. 1A-1F.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 at an intermediate point during fabrication. In this example, the FinFET device 10 includes three illustrative fins 14, an isolation material 15, a gate structure 18, sidewall spacers 20 and a gate cap layer 22. The fins 14 have a three-dimensional configuration: a height H, a width W and an axial length L. The portions of the fins 14 covered by the gate structure 18 are the channel regions of the FinFET device 10, while the portions of the fins 14 positioned laterally outside of the spacers 20 are part of the source/drain regions of the device 10. Although not depicted, the portions of the fins 14 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition. In other applications, trenches may be formed in the portions of the fins 14 in the source/drain regions and an epi semiconductor material may be grown in the trenches so as to form embedded source/drain regions.
FIGS. 1B-1F depict one illustrative process flow for forming the fins 14 using the BOTS technique. FIG. 1B depicts the device 10 after several process operations were performed. First, a patterned hard mask layer 30, e.g., comprised of a patterned layer of silicon nitride (pad-nitride) and a patterned layer of silicon dioxide (pad-oxide), was formed above the substrate 12 in accordance with the desired fin pattern and pitch. Next, an etching process was performed through the patterned hard mask layer 30 so as to define full-depth fin-formation trenches 13 in the substrate 12 that define the fins 14. The fins 14 have a tapered configuration due to the nature of the etching process. The degree of tapering depicted in the drawings may be somewhat exaggerated relative to real-world devices. In general, the fins 14 are comprised of an upper portion having sidewalls 14V and a lower portion having tapered or flared sidewalls 14F.
FIG. 1C depicts the device 10 after several process operations were performed. First, a layer of insulating material 15, such as silicon dioxide, was formed so as to overfill the trenches 13. A chemical mechanical polishing (CMP) process was then performed to planarize the upper surface of the insulating material 15 with the top of the patterned hard mask 30.
FIG. 1D depicts the device 10 after several process operations were performed. First, an etch-back process was performed to recess the layer of insulating material 15 between the fins 14 and thereby expose at least a portion of the upper portions of the fins 14, which corresponds to the final fin height of the fins 14. Next, sidewall spacers 38 were formed adjacent the upper portion of the fins 14 above the recessed layer of insulating material 15.
FIG. 1E depicts the device after an anneal process was performed to oxidize the portions of the fins 14 that are not covered by the spacers 38. This results in the isolation material 15 that vertically separates the fins 14 from the substrate 12. As simplistically depicted in FIGS. 1A and 1E, the BOTS process creates a very uneven surface 12B in the substrate 12. Moreover, using the BOTS process, the thickness 15T of the insulation material 15 is generally relatively thick, e.g., 50-500 nm, and the thickness 15T of the insulation material 15 may vary from fin to fin due to the uneven surface 12B in the substrate 12. Additionally, the BOTS processing sequence is relatively complex and difficult to integrate in a mass production manufacturing environment. FIG. 1F is a TEM photograph showing the device made using the BOTS process.
The present disclosure is directed to various methods of forming fin isolation regions on FinFET semiconductor devices that may solve or reduce one or more of the problems identified above.